Cerebras used its Hot Chips 2026 deep dive in Palo Alto to lay out the two generations of wafer-scale AI accelerators that follow CS-4 — the 2027 CS-5 aimed at 10,000 tokens per second per user on open-weight models, and a CS-6 wafer-scale engine that will attempt 3D stacking of DRAM directly on top of Cerebras logic and SRAM for the first time.
CS-5 Targets 10,000 Tokens Per Second In 2027
CS-5, targeted for 2027, is designed around a next-generation Wafer-Scale Engine slotted into the same Nexus rack platform Cerebras unveiled with CS-4 last week. The company says CS-5 targets up to 10,000 output tokens per second per user on Gemma 4 31B and gpt-oss-120b, and up to 5,000 tokens per second per user on multi-trillion-parameter frontier models such as Kimi and OpenAI's GPT-5.6 Sol, at roughly 3 million tokens per megawatt. The same architecture is designed to support models above 50 trillion parameters while keeping interactive latencies.
CS-6: Wafer-Scale Goes 3D
The bigger architectural jump is CS-6. A Cerebras wafer already occupies 100% of a 300mm silicon disc, so more on-chip memory has to come from stacking — not spreading. CS-6 will integrate wafer-scale SRAM and compute with 3D-stacked DRAM through ultra-high-bandwidth vertical connections, a first for the format. The stated goal is to expand memory capacity dramatically without giving up the on-die locality that makes wafer scale fast, while shrinking system footprints for a given model. Tom's Hardware's coverage notes the concurrent area reduction could also let Cerebras produce more Wafer-Scale Engines from the same 300mm wafer supply — a meaningful constraint as the company chases its target of 600 megawatts of deployed capacity by year-end 2027.
Nexus, Power And The Anti-Cable Argument
Cerebras also detailed the CS-4 Nexus design in more depth, arguing its 53.5 PB/s of on-wafer fabric bandwidth per WSE-3T is more than 200 times the 260 TB/s of scale-up bandwidth in Nvidia's Rubin NVL72 rack — and requires none of the roughly 5,000 internal NVLink cables that Cerebras chief system architect JP Fricker called "a mess" at the conference. Placing AC/DC converters within 0.5mm of the wafer lets CS-4 deliver nearly twice the power at almost the same voltage, feeding directly into the WS-3T's clock speeds and up to 2x the throughput of prior generations. For a company that already runs OpenAI's ultrafast GPT-5.6 Sol tier and has an AMD Helios inference partnership, the CS-5-to-CS-6 roadmap is Cerebras's answer to a market shifting from training to increasingly memory-bound agentic inference.
Reporting based on coverage from Cerebras, Tom's Hardware and ServeTheHome.