SK hynix and California-based TetraMem announced a jointly developed analog in-memory computing (AIMC) chip on July 14, 2026, designed to sidestep the von Neumann bottleneck that has strangled conventional AI accelerators. The device stores neural network weights in non-volatile memristor arrays and runs multiply-accumulate operations directly inside memory, doing away with the constant shuttling of data between DRAM and logic that eats up power in digital GPUs.
How The AIMC Chip Works
By performing calculations with analog signals inside the memory cells themselves, the chip promises significant per-inference energy efficiency gains over conventional digital accelerators and better parallelism for neural network workloads. Executives flagged edge AI, real-time analytics and low-power autonomous systems as target applications; commercial samples are earmarked for select customers later this year. Detailed benchmarks were not disclosed.
Why SK hynix Cares
The AIMC bet slots alongside SK hynix's 12-layer HBM4E samples and its multiyear memory pact with NVIDIA — the company is trying to defend its HBM dominance while betting on adjacent memory-centric architectures. It also lands the same week as SK hynix's $28B Nasdaq uplisting pitch to Western AI investors, giving the company a fresh differentiation story beyond stacking capacity.
The Analog Renaissance
AIMC has been a research darling for a decade; commercial roll-outs have been slower thanks to precision limits and the difficulty of integrating memristor arrays with mainstream CMOS lines. Pairing TetraMem's memristor IP with a hyperscale memory vendor is one of the more credible attempts yet to move AIMC out of the lab. If the chip lands, it could give edge deployments — humanoids, drones, defense sensors — a much lower-wattage inference path.
Reporting based on coverage from Natural News.