Samsung Electronics (KRX: 005930) laid out an ambitious 3D memory roadmap at Future of Memory and Storage 2026 in Santa Clara this week, previewing a concept dubbed zHBM that vertically stacks high-bandwidth memory directly above an AI accelerator and, according to the company, targets roughly eight times the performance of HBM5.
Memory On Top Of The AI Chip
Executives Jin-Yub Lee and Kyungryun Kim used the FMS 2026 keynote to argue that placing HBM alongside the processor no longer keeps pace with hyperscale AI. By using next-generation wafer bonding to place memory directly above the accelerator, Samsung claims zHBM can deliver more than 10x the memory density of HBM5, cut thermal resistance by more than half and triple energy efficiency. zHBM also supports custom interlayer IP so accelerator customers can tailor capacity and I/O.
V10 BV-NAND Crosses 400 Layers
Samsung also unveiled V10 BV-NAND, its first Bonding V-NAND architecture, exactly 13 years after the company introduced V-NAND at the 2013 Flash Memory Summit. The 400-plus-layer node uses wafer bonding to lift storage density about 58% over V9 while improving read, write and I/O performance. Alongside V10 the company introduced zNAND-O, a four- and eight-layer high-performance NAND aimed at real-time edge AI, plus updates to HBM4E samples already shipping to hyperscalers, HBM5, LPDDR5X-PIM and the PM1763 enterprise SSD.
Memory Bottleneck Race Heats Up
The concept unveil arrived the same week rival SK hynix introduced its CMM-Ax CXL-PNM solution with Marvell and its first HBF standard alongside Sandisk. It also shadows Astera Labs' Scorpio AI fabric ramp and Anthropic's move to co-design custom AI silicon with Samsung and Broadcom. Samsung stressed its status as the only integrated device manufacturer offering end-to-end memory, foundry and packaging turnkey solutions, a pitch aimed at accelerator customers deciding how to break AI's memory wall.
Reporting based on coverage from Samsung, TrendForce, StorageReview and VideoCardz.