Taiwan's Alchip Technologies used AI Infra Summit 2026 in Santa Clara to preview a full-stack 2nm ASIC design platform and a complete 3DIC ecosystem built around TSMC's CoWoS packaging, staking a claim on the custom-silicon business that hyperscalers and AI startups are steering away from Nvidia's off-the-shelf GPUs.
2nm in Development, 3nm in Production
Alchip said 3nm designs are already in production for its customers and that 2nm parts are actively in development. The company is also shipping a 3nm I/O chiplet building block that customers can pair with their own compute die, part of what Alchip is pitching as an off-the-shelf multi-die assembly kit instead of a one-off custom project. Alchip has completed more than 650 tape-outs since 2003; roughly 90% of its current work is on sub-7nm nodes.
Chiplet Assembly, Optical Interconnect and Die-to-Die IP
The company is highlighting three IP tracks aimed at hyperscaler silicon teams: high-performance die-to-die interconnect, optical interconnect for scale-up fabrics, and a portfolio of TSMC 3DIC packaging flows covering multiple CoWoS variants. Together, the pieces let a customer bring an AI training or inference part to first silicon without owning a full backend team.
Why It Matters
Custom AI silicon has become one of the fastest-growing lines in the foundry business, with Broadcom, Marvell and Alchip all competing to be the design partner of choice for cloud giants. As alternative AI networking stacks and agentic-AI silicon startups multiply, Alchip's early 2nm and CoWoS readiness turns it into a bottleneck vendor for the next generation of AI factories.
Reporting based on coverage from HPCwire and GlobeNewswire.