Altera and Riverlane Partner to Run Quantum Error Correction on Agilex FPGAs

Altera and Riverlane on September 10, 2026 announced a partnership that validates Riverlane's open-source QECi design example on the Agilex 7 FPGA, giving quantum-hardware developers a low-latency, real-time error-correction reference stack.

Altera and Riverlane Partner to Run Quantum Error Correction on Agilex FPGAs

Altera, the world's largest independent FPGA vendor, and UK quantum-error-correction leader Riverlane on September 10, 2026 announced a partnership that lets quantum-hardware teams build faster, more programmable control and error-correction stacks on Altera silicon. Riverlane also joined the Altera Solutions Acceleration Partner Program (ASAP) to shorten integration cycles for FPGA-based quantum systems.

QECi validated on Agilex 7

Under the deal, Riverlane's QEC Interface (QECi) design example is now validated on an Altera Agilex 7 FPGA. QECi is Riverlane's open, hardware-agnostic protocol that standardises how error-correction data flows between quantum control systems and QEC engines. The reference implementation is published in Riverlane's open-source QECi GitHub repository, giving developers a working starting point for building their own FPGA-based QEC pipelines.

Why Agilex fits QEC workloads

Altera Agilex 7 FPGAs and SoCs ship programmable fabric, high-speed transceivers and 2x-better performance-per-watt than competing 7 nm parts. The Agilex 9 Direct RF FPGA extends that with F-Tile transceivers offering up to 64 Gsps sample rate and 36 GHz RF range — the deterministic, low-latency data movement needed to keep pace with a quantum computer that emits error syndromes every microsecond. "Riverlane's validation of its low-latency QECi protocol on Agilex 7 and Agilex 9 FPGAs demonstrates how our programmable platforms can efficiently connect quantum control and error-correction technologies," said Altera VP of Business Solutions Farhad Shafai.

Altera and Riverlane quantum error correction partnership on Agilex FPGAs

Stacking with the broader QEC race

The move slots alongside the wider industry push for real-time error correction, including the IonQ Walking Cat real-time decoder, Riverlane's own Quantinuum work on gas-turbine simulation and this week's Pasqal-LG CNS neutral-atom pact. For Altera, the deal signals a bid to make FPGAs the de-facto glue layer between classical controllers and increasingly diverse qubit modalities.

Where developers can plug in

Riverlane engineers will demo QECi on Agilex FPGAs at Booth 309 during IEEE Quantum Week 2026, September 13-18 in Toronto. Altera has also published a dedicated quantum-computing solutions page that maps Agilex parts to qubit control, readout and QEC data paths.

Reporting based on coverage from The Quantum Insider, Altera and Riverlane press materials.

Category: Partnerships

Tags: AI Partnership Quantum Computing Semiconductors AI Infrastructure

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