Siemens Digital Industries Software and TSMC used the chipmaker's Open Innovation Platform (OIP) Ecosystem Forum on September 23, 2026 to expand a long-running EDA partnership, adding a jointly developed AI-powered design rule check (DRC) fixing agent and rolling Siemens' Calibre, Aprisa, Solido, Fuse EDA and Innovator3D IC tools across TSMC's most advanced process nodes.
DRC Fixing Agent Cuts Manual Rework
The headline deliverable is an intelligent agent that automates DRC fixing for both digital and custom IC flows. Built on Siemens' Calibre platform and integrated with Aprisa place-and-route and Solido custom design, the agent inspects violation reports, proposes fixes and validates them without a human in the loop for common categories, which Siemens said reduces the manual work engineers spend chasing DRC clean-up before tape-out.
Nodes: N2, N2P, N3C, A16, A14
Siemens' Calibre, mPower, L-Edit and Solido tools have been re-certified against TSMC's N2, N2P and N3C nodes, and enablement is now extending to A16 and A14 — TSMC's 1.6nm-class and 1.4nm-class process nodes on the roadmap. The companies also expanded silicon photonics and 3DFabric packaging support, including new flows for Innovator3D IC Integrator with TSMC's advanced 2.5D and 3D stacks.
Fuse EDA AI System Becomes A Shared Pipeline
The tie-up formalises Fuse EDA AI System — Siemens' agentic EDA framework — as a shared automation layer inside TSMC's OIP. Ankur Gupta, EVP of Siemens EDA, said the combination "is helping customers achieve new levels of productivity, speed and design confidence," while TSMC's Aveek Sarkar said intelligent automation is the way engineers cope with "rising design complexity" at 2nm and below.
Why It Matters
TSMC's N2 node begins volume production in the coming quarters, and hyperscaler AI accelerators are already booking capacity on A16. The Siemens partnership is meant to ensure that Cadence and Synopsys are not the only route to a tape-out at those nodes — a strategically important message as Siemens EDA (the former Mentor Graphics) tries to hold market share in a segment where AI-driven design flows are quickly becoming table stakes.
Related coverage on The Robotics Media: TSMC's 2027 wafer price hike for AI chips, MediaTek's 2nm Dimensity 9600 Pro, and Qualcomm's 2nm Snapdragon 8 Elite Gen 6 Extreme.
Reporting based on coverage from Siemens Newsroom, HPCwire, Evertiq and eeNews Europe.