Diraq Scales Silicon Spin Qubits To Eight On imec's 300mm CMOS Line

Diraq and imec reported the first eight-qubit silicon-spin array built on a 300 mm CMOS foundry line, a 4x jump in array size in under a year with coherence and control fidelity preserved.

Key Takeaways

  • Diraq and imec demonstrated the first eight-qubit silicon spin-qubit array fabricated on a standard 300 mm CMOS foundry line, published in Nature Communications on July 9.
  • The array size grew fourfold in under nine months with no measurable loss of coherence or control fidelity, using exactly the same fabrication process as the earlier two-qubit device.
  • Scaling from two to eight qubits did not require major increases in sensor count, wiring density or thermal load, and single-qubit coherence times were at the upper end of the state of the art for silicon spin qubits.
  • Diraq's roadmap targets hundreds of qubits next, thousands by 2029, and over one million by 2031 — the threshold associated with fault-tolerant, commercially useful quantum computing — in a footprint small enough for a conventional data center.
  • The result's significance is manufacturability rather than applications: eight qubits is still tiny, and Diraq has not yet demonstrated a full logical-qubit-scale error-correction code on the platform.

Diraq Scales Silicon Spin Qubits To Eight On imec's 300mm CMOS Line

Australian silicon-spin-qubit company Diraq and Belgian research center imec have reported the first successful operation of an eight-qubit silicon spin-qubit array fabricated on a standard 300 mm CMOS foundry line, a fourfold jump in array size in under a year with no measurable loss of coherence or control fidelity. The result was published in Nature Communications on July 9 under the title “Eight-Qubit Operation of a 300 mm SiMOS Foundry-Fabricated Device.”

Why 300 mm CMOS matters for quantum

Most quantum-computing hardware today is hand-built in specialty facilities. Diraq’s bet is that silicon spin qubits can ride the same industrial infrastructure that already produces billions of classical chips per year. That means the same 300 mm wafers, the same lithography tools, and the same yield economics that made modern CPUs cheap — instead of the bespoke fabrication used for many superconducting or trapped-ion machines. imec, whose 300 mm SiMOS pilot line built the device, is arguably the only research center in the world that can offer that industrial process today at qubit-grade precision.

imec 300 mm CMOS pilot line in Leuven, Belgium

Scaling without a new machine

The paper shows that Diraq’s eight-qubit device — four pairs of qubits — was tuned and individually addressed with single-qubit coherence times at the upper end of the state of the art for silicon spin qubits. Crucially, the readout architecture did not require a big jump in sensor count, wiring density or thermal load to scale from two qubits to eight. “Nine months ago, we showed the world that our silicon qubits could be built reliably in imec’s 300 mm CMOS line,” said Founder and CEO Andrew Dzurak. “Today, we have scaled the size of the array using exactly the same process, with no compromise in coherence. This is the cadence we need to reach utility scale.”

The 2029 and 2031 roadmap

Diraq now says its next milestone is a device with hundreds of qubits, followed by a target of thousands by 2029 and more than one million by 2031 — the threshold typically associated with fault-tolerant, commercially useful quantum computing. Because the underlying process is CMOS, the physical footprint of that utility-scale machine is projected to remain comparable to today’s eight-qubit device, small enough to sit inside a conventional data center rather than requiring a new class of fab. That is a very different scaling story from neutral-atom architectures or the superconducting stacks running at quantum-AI data centers.

What it does not solve — yet

Eight qubits is still tiny by any application standard, and Diraq has not yet demonstrated a full logical-qubit-scale error-correction code on the platform. The paper’s significance is manufacturability, not applications: it shows the process is reproducible and that scaling does not degrade what the smaller unit cell already achieved. The next public test will be whether Diraq can hit its stated hundreds-of-qubits milestone on the same imec line without new physics — the pattern the semiconductor industry has always followed.

Reporting based on coverage from Nature Communications, The Quantum Insider, Quantum Computing Report and imec.

Category: Machine Learning

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Frequently Asked Questions

Why does building qubits on a 300 mm CMOS line matter?

It means silicon spin qubits can use the same industrial infrastructure — 300 mm wafers, lithography tools and yield economics — that produces billions of classical chips per year, instead of the bespoke fabrication used for many superconducting or trapped-ion machines. imec's SiMOS pilot line is arguably the only facility offering this industrial process at qubit-grade precision today.

Did scaling from two to eight qubits degrade performance?

No. The eight-qubit device, arranged as four pairs of qubits, was tuned and individually addressed with single-qubit coherence times at the upper end of the state of the art for silicon spin qubits, and the readout architecture avoided big jumps in sensor count, wiring or thermal load.

What is Diraq's roadmap to useful quantum computing?

The next milestone is a device with hundreds of qubits, followed by thousands by 2029 and more than one million by 2031, the threshold typically associated with fault-tolerant, commercially useful quantum computing. Because the process is CMOS, the utility-scale machine is projected to fit inside a conventional data center.

What has Diraq not yet demonstrated?

Diraq has not yet demonstrated a full logical-qubit-scale error-correction code on the platform, and eight qubits remains tiny by application standards. The paper's significance is proving the process is reproducible and that scaling does not degrade performance.